VHDL A Language for Specifying Logic (PDF 24p)

EBook Description: VHDL A Language for Specifying Logic (PDF 24p)

An Introduction to Space radiation effects on Microelectronics (PDF 83p)

The Verilog Language (PDF Slides 80p)

Originally a modeling language for a very efficient event-driven digital logic simulator.
Later pushed into use as a specification language for logic
synthesis.
Now, one of the two most commonly-used languages in digital hardware design (VHDL is the other.
Virtually every chip (FPGA, ASIC, etc.) is designed in part using one of these two languages.

Verilog Tutorial (PDF 227p)

Notes on Verilog Tutorial.

Introduction to Verilog (PDF 31p)

Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated circuit(IC) designers. The other one is VHDL.

Handbook on Verilog HDL (PDF 32p)

Verilog HDL is a Hardware Description Language (HDL). A Hardware Description Language is a language used to describe a digital system, for example, a computer or a component of a computer.

The Verilog Golden Reference Guide (PDF 151p)

The Verilog Hardware Description Language (HDL) is a language for
describing the behaviour and structure of electronic circuits, and is an IEEE standard (IEEE Std. 1364-1995).

Verilog HDL Quick Reference Guide (56p)

The following Verilog HDL constructs are independent processes that are evaluated concurrently in simulation time:
� module instances
� primitive instances
� continuous assignments
� procedural blocks

Digital System Design Using VHDL

Notes on Digital System Design Using VHDL.

REVIEW OF VHDL

VHDL begin with double dashes (no space between them) and continue to the end of the current
line.

Introduction to ISE & ModelSim

After design entry (either schematic capture or VHDL entry),
ModelSim (Mentor Graphic Corp.) will be used to simulate and verify the design (with debugging performed as needed).

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