A VHDL tutorial with good examples and links to reference and related material.

EBook Description: HDL (Hardware Description Language) based design has established itself as the modern approach to design of digital systems, with VHDL (VHSIC Hardware Description Language) and Verilog HDL being the two dominant HDLs.

Reference guides and tutorials for VHDL and Verilog.

Verilog information.

Notes on Verilog information.

Combinational Logic Design Process

Combinational Logic Design Process
� Create truth table from specification
� Generate K-maps & obtain logic equations
� Draw logic diagram (sharing common gates)
� Simulate circuit for design verification

Flip-flops and Latches

Notes on Flip-flops and Latches.

Overview of FPGAs

Notes on Field Programmable Gate Arrays.

Introduction to Programmable Logic

Notes on Introduction to Programmable Logic

Configuring Spartan-II FPGAs from Parallel EPROM

Many FPGA users prefer to store configuration data on parallel PROMs because they are available in greater storage capacities than serial PROMs. A parallel PROM stores data as an addressed byte which is accessed by an address bus.

Overview of Boundary Scan and the Boundary Scan Interface in Spartan-2 FPGAs

Developed to test interconnect between chips on PCB
� Originally referred to as JTAG (Joint Test Action Group)
� Uses scan design approach to test external interconnect
� No-contact probe overcomes problem of �in-circuit� test.

PicoBlaze Overview and PicoBlaze Manual and User�s Guide

The PicoBlaze solution consumes
considerably less resources than
comparable 8-bit microcontroller
architectures. It is provided as a
free, source-level VHDL file with
royalty-free re-use within Xilinx
FPGAs. Because it is delivered as VHDL source, the PicoBlaze
microcontroller is immune to product obsolescence as the microcontroller can be retargeted to future generations of Xilinx FPGAs, exploiting future cost reductions and feature enhancements.

INTRODUCTION OF HDLS IN THE DESIGN PROCES

Benefits of HDLs:
� Early design verification via high level design verification
� Evaluation of alternative architectures
� Top-down design (w/synthesis)
� Reduced risk to project due to design errors
� Design capture (w/synthesis & independence of implementation media)

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