Introduction to Programmable Logic

EBook Description: Notes on Introduction to Programmable Logic

Many FPGA users prefer to store configuration data on parallel PROMs because they are available in greater storage capacities than serial PROMs. A parallel PROM stores data as an addressed byte which is accessed by an address bus.

Overview of Boundary Scan and the Boundary Scan Interface in Spartan-2 FPGAs

Developed to test interconnect between chips on PCB
� Originally referred to as JTAG (Joint Test Action Group)
� Uses scan design approach to test external interconnect
� No-contact probe overcomes problem of �in-circuit� test.

PicoBlaze Overview and PicoBlaze Manual and User�s Guide

The PicoBlaze solution consumes
considerably less resources than
comparable 8-bit microcontroller
architectures. It is provided as a
free, source-level VHDL file with
royalty-free re-use within Xilinx
FPGAs. Because it is delivered as VHDL source, the PicoBlaze
microcontroller is immune to product obsolescence as the microcontroller can be retargeted to future generations of Xilinx FPGAs, exploiting future cost reductions and feature enhancements.

INTRODUCTION OF HDLS IN THE DESIGN PROCES

Benefits of HDLs:
� Early design verification via high level design verification
� Evaluation of alternative architectures
� Top-down design (w/synthesis)
� Reduced risk to project due to design errors
� Design capture (w/synthesis & independence of implementation media)

VHDL ENTITIES, ARCHITECTURES, AND PROCESS

NOTES on VHDL ENTITIES, ARCHITECTURES, AND PROCESS.

VHDL IDENTIFIERS, SIGNALS, & ATTRIBUTES

NOTES ON VHDL IDENTIFIERS, SIGNALS, & ATTRIBUTES.

VHDL OPERATORS

NOTES on VHDL OPERATORS.

VHDL CONSTRUCT

NOTES on VHDL CONSTRUCT.

VHDL HIERARCHICAL MODELINN

Notes on VHDL HIERARCHICAL MODELING.

VHDL Modeling Guidelines

Notes on VHDL Modeling Guidelines.

• Free IAS eBooks
• Free GRE eBooks
• Free MBA eBooks
• Free GATE eBooks