INTRODUCTION OF HDLS IN THE DESIGN PROCES
Benefits of HDLs: • Early design verification via high level design verification • Evaluation of alternative architectures • Top-down design (w/synthesis) • Reduced risk to project due to design errors • Design capture (w/synthesis & independence of implementation media)
VHDL ENTITIES, ARCHITECTURES, AND PROCESS
NOTES on VHDL ENTITIES, ARCHITECTURES, AND PROCESS.
VHDL IDENTIFIERS, SIGNALS, & ATTRIBUTES
NOTES ON VHDL IDENTIFIERS, SIGNALS, & ATTRIBUTES.
VHDL OPERATORS
NOTES on VHDL OPERATORS.
VHDL CONSTRUCT
NOTES on VHDL CONSTRUCT.
VHDL HIERARCHICAL MODELINN
Notes on VHDL HIERARCHICAL MODELING.
VHDL Modeling Guidelines
Notes on VHDL Modeling Guidelines.
FSMs in VHDL Using Enumeration Data Types
This FSM is a Moore machine since its outputs (RST and SHIFT) are a function of the current state only.
RAMs Models in VHD
Notes on RAMs Models in VHDL.
PSIM: Processor SIMulator (version 4.2)
A simulator for a basic stored program computer architecture is described which graphically displays the architecture while showing the detailed operation on a per clock cycle basis. The instruction set consists of sixteen instructions that can be combined to form many capabilities including conditional branching.
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