The Hamburg VHDL Archive - lots of stuff here including a good look at libraries and packages.: Since the early 80's our institute has been member of different research activities and projects dealing with system- and VLSI-design.

Date Added: 7/30/2011 1:29:36 AM | Visits: 31327

VHDL Cookbook - a 111 page PDF pre-published version of The Designer's Guide to VHDL: VHDL is a language for describing digital electronic systems. It arose
out of the United States Government�s Very High Speed Integrated Circuits
(VHSIC) program, initiated in 1980.

Date Added: 7/30/2011 1:28:22 AM | Visits: 31184

A comprehensive set of overviews of VHDL, Verilog, System C, PERL, and TCL/TK:: Notes on A comprehensive set of overviews of VHDL, Verilog, System C, PERL, and TCL/TK.

Date Added: 7/30/2011 1:23:26 AM | Visits: 33167

VHDL & Verilog Compared & Contrasted Plus Modeled Example Written in VHDL, Verilog and C: There are now two industry standard hardware description languages, VHDL and Verilog. The complexity of ASIC and FPGA designs has meant an increase in the number of specialist design consultants with specific tools and with their own libraries of macro and mega cells written in either VHDL or Verilog. As a result, it is important that designers know both VHDL and Verilog and that EDA tools vendors provide tools that provide an environment allowing both languages to be used in unison.

Date Added: 7/30/2011 1:21:23 AM | Visits: 33592

Introduction to ISE & ModelSim: After design entry (either schematic capture or VHDL entry),
ModelSim (Mentor Graphic Corp.) will be used to simulate and verify the design (with debugging performed as needed).

Date Added: 7/30/2011 1:18:45 AM | Visits: 31833

REVIEW OF VHDL: VHDL begin with double dashes (no space between them) and continue to the end of the current
line.

Date Added: 7/30/2011 1:15:11 AM | Visits: 32917

Digital System Design Using VHDL: Notes on Digital System Design Using VHDL.

Date Added: 7/30/2011 1:06:11 AM | Visits: 32783

Verilog Tutorial (PDF 227p): Notes on Verilog Tutorial.

Date Added: 7/29/2011 12:17:07 AM | Visits: 32208

The Verilog Language (PDF Slides 80p): Originally a modeling language for a very efficient event-driven digital logic simulator.
Later pushed into use as a specification language for logic
synthesis.
Now, one of the two most commonly-used languages in digital hardware design (VHDL is the other.
Virtually every chip (FPGA, ASIC, etc.) is designed in part using one of these two languages.

Date Added: 7/29/2011 12:14:37 AM | Visits: 32572

Verilog HDL Quick Reference Guide (56p): The following Verilog HDL constructs are independent processes that are evaluated concurrently in simulation time:
� module instances
� primitive instances
� continuous assignments
� procedural blocks

Date Added: 7/29/2011 12:11:35 AM | Visits: 32151