PSIM: Processor SIMulator (version 4.2): A simulator for a basic stored program computer architecture is described which graphically displays the architecture while showing the detailed operation on a per clock cycle basis. The instruction set consists of sixteen instructions that can be combined to form many capabilities including conditional branching.

Date Added: 7/30/2011 4:41:04 AM | Visits: 32190

RAMs Models in VHD: Notes on RAMs Models in VHDL.

Date Added: 7/30/2011 4:32:25 AM | Visits: 31333

FSMs in VHDL Using Enumeration Data Types: This FSM is a Moore machine since its outputs (RST and SHIFT) are a function of the current state only.

Date Added: 7/30/2011 4:28:46 AM | Visits: 33065

VHDL Modeling Guidelines: Notes on VHDL Modeling Guidelines.

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VHDL HIERARCHICAL MODELINN: Notes on VHDL HIERARCHICAL MODELING.

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VHDL CONSTRUCT: NOTES on VHDL CONSTRUCT.

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VHDL OPERATORS: NOTES on VHDL OPERATORS.

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VHDL IDENTIFIERS, SIGNALS, & ATTRIBUTES: NOTES ON VHDL IDENTIFIERS, SIGNALS, & ATTRIBUTES.

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VHDL ENTITIES, ARCHITECTURES, AND PROCESS: NOTES on VHDL ENTITIES, ARCHITECTURES, AND PROCESS.

Date Added: 7/30/2011 4:06:14 AM | Visits: 31603

INTRODUCTION OF HDLS IN THE DESIGN PROCES: Benefits of HDLs:
� Early design verification via high level design verification
� Evaluation of alternative architectures
� Top-down design (w/synthesis)
� Reduced risk to project due to design errors
� Design capture (w/synthesis & independence of implementation media)

Date Added: 7/30/2011 4:04:46 AM | Visits: 33635